(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to the formation of ultra-shallow buried-channel MOSFETs.
(2) Description of the Prior Art
In integrated circuit applications such as 256 Megabit or larger dynamic random access memories (DRAM), very small feature sizes, down to the 0.18 micron regime, are required. Additionally, very short gate delays, as low as 40 picoseconds, are required to achieve the switching speeds needed. In these regimes, very small MOS transistors, and more specifically, buried-channel MOS transistors are used. Techniques to reduce the size, or scaling, of buried-channel transistors bring great challenges.
When compared with surface channel MOS transistors, buried-channel MOS can provide the advantage of higher switching speeds due to higher carrier mobility. Additionally, the extended use of N+ polysilicon gates to form PMOS buried-channel transistors can simplify the manufacturing process and keep costs low. Due to these advantages, it is common in the art to use buried-channel MOS, and specifically PMOS, in very high density, very high speed integrated circuits. Unfortunately, buried-channel devices suffer from more severe short-channel effects than surface channel devices. A new fabrication process is proposed in this invention to overcome the short channel effects problem and to successfully implement a sub-0.25 micron buried-channel PMOS transistor.
To fabricate a very small and very high-speed buried-channel device a method to create an ultra-shallow counter-doped channel must be used. To achieve both higher speed at a lower supply voltage and higher memory capacity at smaller chip size, the device channel length and threshold voltage must be reduced. Specifically, a reduced threshold voltage requires that the buried-channel junction concentration must be increased. Unfortunately, this leads to greater leakage currents and punch-through effects. To offset these problems the junction must therefore be made very shallow. It is desirable that the device has a channel length of less than 0.25 microns and a threshold voltage of less than 0.65V. To achieve these specifications for a p-channel MOSFET, for example, the counter-doped channel must be less than 0.04 microns in depth with a doping concentration exceeding 10.sup.18 cm.sup.-3.
Typically in the art, creating such an ultra-shallow counter-doped p-channel would require an ultra-low energy implant of ions such as B.sup.11 or BF.sub.2. Such an approach requires the manufacturing plant to invest in an ultra-low energy implanter and in rapid thermal processing (RTP) equipment. Another approach that has been proposed is the use of a pre-amorphization step. This technique has the disadvantage of the implant inducing surface states and junction leakage. Yet another strategy is to implant ions with heavy masses, such as B.sub.10 H.sub.14 and I.sup.49. The drawbacks with this approach are the scarcity of the implant sources and the difficulty of activating the ion species. Another approach to creating ultra-shallow junctions is to implant through the gate oxide. However, this compromises the integrity of the gate oxide. Finally, an epitaxial technique could be used to grow a counter-doped layer. This would be incompatible with the standard CMOS processing used in the formation of the integrated circuit.
Several prior art approaches attempt to create device junctions in unique ways or attempt to form very small MOSFET devices that are less prone to short-channel effects. U.S. Pat. No. 5,737,964 to Hsu et al shows a method of doping the source, drain, and polysilicon gate of a thin film transistor using a doped silicate glass (PSG or BSG) layer. Ions are diffused up into the polysilicon gate and the thin film silicon to form the source and drain. This patent discloses a thin film transistor process and does not use the doped silicate glass to form the transistor channel. U.S. Pat. No. 5,792,699 to Tsui shows a method for forming a p-channel MOSFET using an ion implant after the polysilicon gate and the source and drain regions are formed. U.S. Pat. No. 5,766,998 to Tseng displays an ion implanted channel stop process where the source and drain regions are formed by diffusion of ions from the doped polysilicon. U.S. Pat. No. 4,824,797 to Goth shows a self-aligned punch through region.